#ifndef __RK3288_RESET_H__
#define __RK3288_RESET_H__

#ifdef __cplusplus
extern "C" {
#endif

#define RK3288_RESET_CORE0				(0)
#define RK3288_RESET_CORE1				(1)
#define RK3288_RESET_CORE2				(2)
#define RK3288_RESET_CORE3				(3)
#define RK3288_RESET_CORE0_PO			(4)
#define RK3288_RESET_CORE1_PO			(5)
#define RK3288_RESET_CORE2_PO			(6)
#define RK3288_RESET_CORE3_PO			(7)
#define RK3288_RESET_PDCORE_STRSYS		(8)
#define RK3288_RESET_PDBUS_STRSYS		(9)
#define RK3288_RESET_L2C				(10)
#define RK3288_RESET_TOPDBG				(11)
#define RK3288_RESET_CORE0_DBG			(12)
#define RK3288_RESET_CORE1_DBG			(13)
#define RK3288_RESET_CORE2_DBG			(14)
#define RK3288_RESET_CORE3_DBG			(15)

#define RK3288_RESET_PDBUG_AHB_ARBITOR	(16)
#define RK3288_RESET_EFUSE256			(17)
#define RK3288_RESET_DMAC1				(18)
#define RK3288_RESET_INTMEM				(19)
#define RK3288_RESET_ROM				(20)
#define RK3288_RESET_SPDIF8CH			(21)
#define RK3288_RESET_TIMER				(22)
#define RK3288_RESET_I2S0				(23
#define RK3288_RESET_SPDIF				(24)
#define RK3288_RESET_TIMER0				(25)
#define RK3288_RESET_TIMER1				(26)
#define RK3288_RESET_TIMER2				(27)
#define RK3288_RESET_TIMER3				(28)
#define RK3288_RESET_TIMER4				(29)
#define RK3288_RESET_TIMER5				(30)
#define RK3288_RESET_EFUSE				(31)

#define RK3288_RESET_GPIO0				(32)
#define RK3288_RESET_GPIO1				(33)
#define RK3288_RESET_GPIO2				(34)
#define RK3288_RESET_GPIO3				(35)
#define RK3288_RESET_GPIO4				(36)
#define RK3288_RESET_GPIO5				(37)
#define RK3288_RESET_GPIO6				(38)
#define RK3288_RESET_GPIO7				(39)
#define RK3288_RESET_GPIO8				(40)
#define RK3288_RESET_I2C0				(42)
#define RK3288_RESET_I2C1				(43)
#define RK3288_RESET_I2C2				(44)
#define RK3288_RESET_I2C3				(45)
#define RK3288_RESET_I2C4				(46)
#define RK3288_RESET_I2C5				(47)

#define RK3288_RESET_DWPWM				(48)
#define RK3288_RESET_MMC_PERI			(49)
#define RK3288_RESET_PERIPH_MMU			(50)
#define RK3288_RESET_DAP				(51)
#define RK3288_RESET_DAP_SYS			(52)
#define RK3288_RESET_TPIU				(53)
#define RK3288_RESET_PMU_APB			(54)
#define RK3288_RESET_GRF				(55)
#define RK3288_RESET_PMU				(56)
#define RK3288_RESET_PERIPH_AXI			(57)
#define RK3288_RESET_PERIPH_AHB			(58)
#define RK3288_RESET_PERIPH_APB			(59)
#define RK3288_RESET_PERIPH_NIU			(60)
#define RK3288_RESET_PDPERI_AHB_ARBI	(61)
#define RK3288_RESET_EMEM				(62)
#define RK3288_RESET_USB_PERI			(63)

#define RK3288_RESET_DMAC2				(64)
#define RK3288_RESET_MAC				(66)
#define RK3288_RESET_GPS				(67)
#define RK3288_RESET_RKPWM				(69)
#define RK3288_RESET_CCP				(71)
#define RK3288_RESET_USBHOST0			(72)
#define RK3288_RESET_HSIC				(73)
#define RK3288_RESET_HSIC_AUX			(74)
#define RK3288_RESET_HSIC_PHY			(75)
#define RK3288_RESET_HSADC				(76)
#define RK3288_RESET_NANDC0				(77)
#define RK3288_RESET_NANDC1				(78)

#define RK3288_RESET_TZPC				(80)
#define RK3288_RESET_SPI0				(83)
#define RK3288_RESET_SPI1				(84)
#define RK3288_RESET_SPI2				(85)
#define RK3288_RESET_SARADC				(87)
#define RK3288_RESET_PDALIVE_NIU		(88)
#define RK3288_RESET_PDPMU_INTMEM		(89)
#define RK3288_RESET_PDPMU_NIU			(90)
#define RK3288_RESET_SGRF				(91)

#define RK3288_RESET_VIO_ARBI			(96)
#define RK3288_RESET_RGA_NIU			(97)
#define RK3288_RESET_VIO0_NIU_AXI		(98)
#define RK3288_RESET_VIO_NIU_AHB		(99)
#define RK3288_RESET_LCDC0_AXI			(100)
#define RK3288_RESET_LCDC0_AHB			(101)
#define RK3288_RESET_LCDC0_DCLK			(102)
#define RK3288_RESET_VIO1_NIU_AXI		(103)
#define RK3288_RESET_VIP				(104)
#define RK3288_RESET_RGA_CORE			(105)
#define RK3288_RESET_IEP_AXI			(106)
#define RK3288_RESET_IEP_AHB			(107)
#define RK3288_RESET_RGA_AXI			(108)
#define RK3288_RESET_RGA_AHB			(109)
#define RK3288_RESET_ISP				(110)
#define RK3288_RESET_EDP				(111)

#define RK3288_RESET_VCODEC_AXI			(112)
#define RK3288_RESET_VCODEC_AHB			(113)
#define RK3288_RESET_VIO_H2P			(114)
#define RK3288_RESET_MIPIDSI0			(115)
#define RK3288_RESET_MIPIDSI1			(116)
#define RK3288_RESET_MIPICSI			(117)
#define RK3288_RESET_LVDS_PHY			(118)
#define RK3288_RESET_LVDS_CON			(119)
#define RK3288_RESET_GPU				(120)
#define RK3288_RESET_HDMI				(121)
#define RK3288_RESET_CORE_PVTM			(124)
#define RK3288_RESET_GPU_PVTM			(125)

#define RK3288_RESET_MMC0				(128)
#define RK3288_RESET_SDIO0				(129)
#define RK3288_RESET_SDIO1				(130)
#define RK3288_RESET_EMMC				(131)
#define RK3288_RESET_USBOTG_AHB			(132)
#define RK3288_RESET_USBOTG_PHY			(133)
#define RK3288_RESET_USBOTG_CON			(134)
#define RK3288_RESET_USBHOST0_AHB		(135)
#define RK3288_RESET_USBHOST0_PHY		(136)
#define RK3288_RESET_USBHOST0_CON		(137)
#define RK3288_RESET_USBHOST1_AHB		(138)
#define RK3288_RESET_USBHOST1_PHY		(139)
#define RK3288_RESET_USBHOST1_CON		(140)
#define RK3288_RESET_USB_ADP			(141)
#define RK3288_RESET_ACC_EFUSE			(142)

#define RK3288_RESET_CORESIGHT			(144)
#define RK3288_RESET_PD_CORE_AHB_NOC	(145)
#define RK3288_RESET_PD_CORE_APB_NOC	(146)
#define RK3288_RESET_PD_CORE_MP_AXI		(147)
#define RK3288_RESET_GIC				(148)
#define RK3288_RESET_LCDC_PWM0			(149)
#define RK3288_RESET_LCDC_PWM1			(150)
#define RK3288_RESET_VIO0_H2P_BRG		(151)
#define RK3288_RESET_VIO1_H2P_BRG		(152)
#define RK3288_RESET_RGA_H2P_BRG		(153)
#define RK3288_RESET_HEVC				(154)
#define RK3288_RESET_TSADC				(159)

#define RK3288_RESET_DDRPHY0			(160)
#define RK3288_RESET_DDRPHY0_APB		(161)
#define RK3288_RESET_DDRCTRL0			(162)
#define RK3288_RESET_DDRCTRL0_APB		(163)
#define RK3288_RESET_DDRPHY0_CTRL		(164)
#define RK3288_RESET_DDRPHY1			(165)
#define RK3288_RESET_DDRPHY1_APB		(166)
#define RK3288_RESET_DDRCTRL1			(167)
#define RK3288_RESET_DDRCTRL1_APB		(168)
#define RK3288_RESET_DDRPHY1_CTRL		(169)
#define RK3288_RESET_DDRMSCH0			(170)
#define RK3288_RESET_DDRMSCH1			(171)
#define RK3288_RESET_CRYPTO				(174)
#define RK3288_RESET_C2C_HOST			(175)

#define RK3288_RESET_LCDC1_AXI			(176)
#define RK3288_RESET_LCDC1_AHB			(177)
#define RK3288_RESET_LCDC1_DCLK			(178)
#define RK3288_RESET_UART0				(179)
#define RK3288_RESET_UART1				(180)
#define RK3288_RESET_UART2				(181)
#define RK3288_RESET_UART3				(182)
#define RK3288_RESET_UART4				(183)
#define RK3288_RESET_SIMC				(186)
#define RK3288_RESET_PS2C				(187)
#define RK3288_RESET_TSP				(188)
#define RK3288_RESET_TSP_CLKIN0			(189)
#define RK3288_RESET_TSP_CLKIN1			(190)
#define RK3288_RESET_TSP_27M			(191)

#ifdef __cplusplus
}
#endif

#endif /* __RK3288_RESET_H__ */
